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1 lt1186f dac programmable ccfl switching regulator (bits-to-nits tm ) features n wide battery input range: 4.5v to 30v n grounded lamp or floating lamp configurations n open lamp protection n precision 50 m a full-scale dac programming current n standard spi mode or pulse mode n dac setting is retained in shutdown face modes including standard spi mode and pulse mode. on power-up, the dac counter resets to half-scale and the dac configures to spi or pulse mode depending on the cs signal level. in spi mode, the system microprocessor serially transfers the present 8-bit data and reads back the previous 8-bit data. in pulse mode, the upper six bits of the dac configure as increment-only (1-wire interface) or increment/decrement (2-wire interface) operation depend- ing on the d in signal level. the lt1186f control circuitry operates from a logic supply voltage of 3.3v or 5v. the ic also has a battery supply voltage pin that operates from 4.5v to 30v. the lt1186f draws 6ma typical quiescent current. an active low shut- down pin reduces total supply current to 35 m a for standby operation and the dac retains its last setting. a 200khz switching frequency minimizes magnetic component size. current mode switching techniques with cycle-by-cycle limiting gives high reliability and simple loop frequency compensation. the lt1186f is available in a 16-pin nar- row so package. n notebook and palmtop computers n portable instruments n retail terminals applicatio n s u the lt ? 1186f is a fixed frequency, current mode, switch- ing regulator that provides the control function for cold cathode fluorescent lighting (ccfl). the ic includes an efficient high current switch, an oscillator, output drive logic, control circuitry and a micropower 8-bit 50 m a full- scale current output dac. the dac provides simple bits- to-lamp current control and communicates in two inter- descriptio n u typical applicatio n u , ltc and lt are registered trademarks of linear technology corporation. bits-to-nits is a trademark of linear technology corporation. 1 nit = 1 candela/meter 2 90% efficient floating ccfl with 1-wire (increment only) pulse mode control of lamp current bat 8v to 28v 16 15 14 13 12 11 10 9 i ccfl dio ccfl v c agnd shdn clk ccfl v sw bulb bat royer v cc i out d out ccfl pgnd cs lt1186f lamp up to 6ma 10 6 l1 r1 750 w l2 100 m h 321 5 4 + + c7, 1 m f c1* 0.068 m f c5 1000pf r2 220k r3 100k c3a 2.2 m f 35v c4 2.2 m f v in 3.3v or 5v lt1186f ?ta01 c3b 2.2 m f 35v c2 27pf 3kv + q2* q1* shutdown aluminum electrolytic is recommended for c3a and c3b. make 3cb esr 3 0.5 w to prevent damage to the lt1186f high-side sense resistor due to surge currents at turn-on c1 must be a low loss capacitor, c1 = wima mkp-20 q1, q2 = zetex ztx849 or rohm 2sc5001 0 m a to 50 m a i ccfl current gives 0ma to 6ma lamp current for a typical display. for additional ccfl/lcd contrast application circuits, refer to the lt1182/83/84/84f data sheet d1 bat85 d in from mpu 1 2 3 4 5 6 7 8 d1 1n5818 l1 = coiltronics ctx210605 l2 = coiltronics ctx100-4 * do not substitute components coiltronics (407) 241-7876 ccfl backlight application circuits contained in this data sheet are covered by u.s. patent number 5408162 and other patents pending
2 lt1186f absolute m axi m u m ratings w ww u v cc ........................................................................... 7v bat, royer, bulb .................................................. 30v ccfl v sw ............................................................... 60v shutdown ................................................................. 6v i ccfl input current .............................................. 10ma dio input current (peak, < 100ms) .................... 100ma digital inputs ................................ C 0.3v to v cc + 0.3v digital outputs .............................. C 0.3v to v cc + 0.3v dac output voltage ....................... C 20v to v cc + 0.3v junction temperature (note 1) ........................... 100 c operating ambient temperature range lt1186fc ............................................ 0 c to 100 c lt1186fi .......................................... C 40 c to 100 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................ 300 c t jmax = 100 c, q ja = 100 c/w lt1186fcs lt1186fis order part number package/order i n for m atio n w u u consult factory for industrial and military grade parts. top view s package 16-lead plastic so 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ccfl pgnd i ccfl dio ccfl v c agnd shdn clk cs ccfl v sw bulb bat royer v cc i out d out d in xsymbol parameter conditions min typ max units i q supply current 3v v cc 6.5v, 1/2 full-scale dac output current l 6 9.5 ma i shdn shutdown supply current shutdown = 0v, ccfl v c open (note 2) 35 70 m a shutdown input bias current shutdown = 0v, ccfl v c = open 5 10 m a shutdown threshold voltage l 0.45 0.85 1.2 v f switching frequency measured at ccfl v sw , i sw = 50ma, 175 200 225 khz i ccfl = 100 m a, ccfl v c = open l 160 200 240 khz dc(max) maximum switch duty cycle measured at ccfl v sw 80 85 % l 75 85 % bv switch breakdown voltage measured at ccfl v sw 60 70 v switch leakage current v sw = 12v, measured at ccfl v sw 20 m a v sw = 30v, measured at ccfl v sw 40 m a i ccfl summing voltage 3v v cc 6.5v 0.425 0.465 0.505 v l 0.385 0.465 0.555 v d i ccfl summing voltage for i ccfl = 0 m a to 100 m a515mv d input programming current ccfl v c offset sink current ccfl v c = 1.5v, positive current measured into pin C 5 5 15 m a d ccfl v c source current for i ccfl = 25 m a, 50 m a, 75 m a, 100 m a, l 4.70 4.95 5.20 m a/ m a d i ccfl programming current ccfl v c = 1.5v t j < 0 c l 4.60 4.95 5.20 m a/ m a ccfl v c to dio current servo ratio dio = 5ma out of pin, measure i(v c ) at ccfl v c = 1.5v l 94 99 104 m a/ma ccfl v c low clamp voltage v bat C v bulb = bulb protect servo voltage l 0.1 0.3 v ccfl v c high clamp voltage i ccfl = 100 m a l 1.7 2.1 2.4 v ccfl v c switching threshold ccfl v sw dc = 0% l 0.6 0.95 1.3 v electrical characteristics t a = 25 c, v cc = shutdown = d in = cs = 3.3v, bat = royer = bulb = 12v, i ccfl = ccfl v sw = open, d out = three-state, dio = i out = clk = gnd, ccfl v c = 0.5v, unless otherwise specified.
3 lt1186f t a = 25 c, v cc = shutdown = d in = cs = 3.3v, bat = royer = bulb = 12v, i ccfl = ccfl v sw = open, d out = three-state, dio = i out = clk = gnd, ccfl v c = 0.5v, unless otherwise specified. electrical characteristics symbol parameter conditions min typ max unit ccfl high-side sense servo current i ccfl = 100 m a, i(v c ) = 0 m a at ccfl v c = 1.5v l 0.93 1.00 1.07 a t j < 0 c l 0.91 1.00 1.07 a ccfl high-side sense servo current bat = 5v to 30v, i ccfl = 100 m a, 0.1 0.16 %/v line regulation i(v c ) = 0 m a at ccfl v c = 1.5v ccfl high-side sense supply current current measured into bat and royer pins l 50 100 150 m a bulb protect servo voltage i ccfl = 100 m a, i(v c ) = 0 m a at ccfl v c = 1.5v, l 6.5 7.0 7.5 v servo voltage measured between bat and bulb pins bulb input bias current i ccfl = 100 m a, i(v c ) = 0 m a at ccfl v c = 1.5v 5 9 m a i lim ccfl switch current limit duty cycle = 50% l 1.25 1.9 3.0 a duty cycle = 75% (note 3) l 0.9 1.6 2.6 a v sat ccfl switch on resistance ccfl i sw = 1a l 0.6 1.0 w d i q supply current increase during ccfl i sw = 1a 20 30 ma/a d i sw ccfl switch on time dac resolution 8 bits dac full-scale current v(i out ) = 0.465v, measured in spi mode 48.5 50 51.5 m a l 47.0 50 53.0 m a dac zero scale current v(i out ) = 0.465v, measured in spi mode 200 na dac differential nonlinearity l 2.0 lsb dac supply voltage rejection 3v v cc 6.5v, i out = full scale, v(i out ) = 0.465v l 24 lsb logic input current 0v v in v cc l 1 m a v ih high level input voltage v cc = 3.3v l 1.9 v v cc = 5v l 2v v il low level input voltage v cc = 3.3v l 0.45 v v cc = 5v l 0.80 v v oh high level output voltage v cc = 3.3v, i o = 400 m a l 2.1 v v cc = 5v, i o = 400 m a l 2.4 v v ol low level output voltage v cc = 3.3v, i o = 1ma l 0.4 v v cc = 5v, i o = 2ma l 0.4 v i oz three-state output leakage v cs = v cc l 5 m a serial interface (notes 4, 5) f clk clock frequency l 2 mhz t cks setup time, clk before cs l 150 ns t css setup time, cs before clk - l 400 ns t dv cs to d out valid see test circuits l 150 ns t ds data in setup time before clk - l 150 ns t dh data in hold time after clk - l 150 ns t do clk to d out valid see test circuits l 150 ns t ckhi clk high time l 200 ns t cklo clk low time l 250 ns t csh clk before cs - l 150 ns t dz cs - to d out in hi-z see test circuits l 400 ns t ckh cs - before clk - l 400 ns
4 lt1186f electrical characteristics t a = 25 c, v cc = shutdown = d in = cs = 3.3v, bat = royer = bulb = 12v, i ccfl = ccfl v sw = open, d out = three-state, dio = i out = clk = gnd, ccfl v c = 0.5v, unless otherwise specified. the l denotes specifications which apply over the specified operating temperature range. note 1: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formula: lt1186fcs: t j = t a + (p d )(100 c/w) note 2: does not include switch leakage. note 3: for duty cycles (dc) between 50% and 80%, minimum guaranteed switch current is given by i lim = 1.4(1.393 C dc) for the lt1186f due to internal slope compensation circuitry. note 4 : timings for all input signals are measured at 0.8v for a high-to- low transition and 2.0v for a low-to-high transition. note 5 : timings are guaranteed but not tested. temperature ( c) ?5 supply current (ma) 6 8 10 9 7 5 3 1 125 lt1186f ?g01 4 2 0 ?5 50 0 50 100 150 25 75 175 supply current vs temperature temperature ( c) 0 shutdown input bias current ( m a) 2 4 6 5 3 1 25 25 75 125 lt1186f ?g03 175 ?0 ?5 0 50 100 150 v cc = 5v v cc = 3v temperature ( c) ?5 shutdown current ( m a) 60 8o 100 90 70 50 30 10 125 lt1186f ?g02 40 20 0 ?5 50 0 50 100 150 25 75 175 v cc = 5v v cc = 3v shutdown current vs temperature shutdown input bias current vs temperature typical perfor m a n ce characteristics u w shutdown threshold voltage vs temperature temperature ( c) 0.6 shutdown threshold voltage (v) 0.8 1.0 1.2 1.1 0.9 0.7 25 25 75 125 lt1186f ?g04 175 ?0 ?5 0 50 100 150 temperature ( c) ?5 ccfl frequency (khz) 220 240 125 lt1186f ?g05 200 180 160 ?5 25 75 175 210 230 190 170 100 ?0 0 50 150 frequency vs temperature temperature ( c) ?5 ccfl maximum duty cycle (%) 87 91 95 93 89 85 81 77 125 150 lt1186f ?g06 83 79 75 ?5 0 ?0 25 50 75 100 175 maximum duty cycle vs temperature symbol parameter conditions min typ max unit serial interface (notes 4, 5) t cslo cs low time f clk = 2mhz l 4550 ns t cshi cs high time l 400 ns
5 lt1186f typical perfor m a n ce characteristics u w temperature ( c) i ccfl summing voltage (v) 0.53 0.52 0.51 0.50 0.49 0.48 0.47 0.46 0.45 0.44 0.43 0.42 0.41 0.40 0.39 0.38 25 25 75 125 lt1186f ?g07 175 ?0 ?5 0 50 100 150 i ccfl summing voltage vs temperature i ccfl summing voltage load regulation i ccfl programming current ( m a) 5 4 3 2 1 0 ? ? ? ? ? ? ? ? ? ?0 40 80 120 160 lt1186f ?g08 200 20 0 60 100 140 180 t = 55 c t = 25 c t = 125 c d i ccfl summing voltage (mv) d ccfl v c source current for d i ccfl programming current vs temperature temperature ( c) 4.80 d ccfl v c source current for d i ccfl programming current ( m a/ m a) 4.90 4.85 5.00 4.95 5.10 5.05 25 25 75 125 lt1186f ?g10 175 ?0 ?5 0 50 100 150 i ccfl = 10 m a i ccfl = 50 m a i ccfl = 100 m a negative dio voltage vs temperature temperature ( c) ?5 negative dio voltage (v) 1.2 1.6 125 lt1186f ?g12 0.8 0.4 0 ?5 25 75 175 1.0 1.4 0.6 0.2 100 ?0 0 50 150 i(dio) = 1ma i(dio) = 5ma i(dio) = 10ma v c sink offset current vs temperature temperature ( c) ? ccfl v c sink offset current ( m a) ? 1 0 ? 10 9 6 8 7 5 3 2 4 ?5 125 150 ?5 0 ?0 25 50 75 100 175 ccfl v c = 0.5v ccfl v c = 1.0v ccfl v c = 1.5v lt1186f ?g09 temperature ( c) ?5 ccfl v c dio current servo ratio ( m a/ma) 101 103 125 lt1186f ?g13 99 97 95 25 25 75 175 100 102 98 96 100 ?0 0 50 150 i(dio) = 1ma i(dio) = 5ma i(dio) = 10ma v c to dio current servo ratio vs temperature temperature ( c) ?5 1.7 ccfl v c high clamp voltage (v) 1.8 2.0 2.1 2.2 2.4 ?0 50 100 lt1186f ?g15 1.9 2.3 25 150 175 ?5 0 75 125 v c high clamp voltage vs temperature v c low clamp voltage vs temperature temperature ( c) 0 ccfl v c low clamp voltage (v) 0.10 0.05 0.20 0.15 0.30 0.25 ?5 25 75 125 lt1186f ?g14 175 ?0 ?5 0 50 100 150 positive dio voltage vs temperature temperature ( c) 0 positive dio voltage (v) 0.4 0.2 0.8 0.6 1.2 1.0 25 25 75 125 lt1186f ?g11 175 ?0 ?5 0 50 100 150 i(dio) = 1ma i(dio) = 5ma i(dio) = 10ma
6 lt1186f typical perfor m a n ce characteristics u w bulb input bias current vs temperature high-side sense null current line regulation vs temperature v c switching threshold vs temperature temperature ( c) ?5 0.6 ccfl v c switching threshold voltage (v) 0.7 0.9 1.0 1.1 1.3 ?0 50 100 lt1186f ?g16 0.8 1.2 25 150 175 ?5 0 75 125 temperature ( c) bulb input bias current ( m a) 6 8 10 lt1186f ?g18 4 2 0 ?5 125 150 ?5 0 ?0 25 50 75 100 175 high-side sense supply current vs temperature temperature ( c) ?5 ccfl high-side sense supply current ( m a) 110 130 150 140 120 100 80 60 125 150 lt1186f ?g19 90 70 50 ?5 0 ?0 25 50 75 100 175 temperature ( c) 0.940 ccfl high-side sense null current (a) 0.980 0.960 1.020 1.000 1.060 1.040 ?5 25 75 125 lt1186f ?g20 175 ?0 ?5 0 50 100 150 high-side sense null current vs temperature temperature ( c) ?5 ccfl high-side sense line regulati0n (%v) 0.120 0.160 125 lt1186f ?g21 0.080 0.040 0.000 25 25 75 175 0.100 0.140 0.060 0.020 100 ?0 0 50 150 switch current (a) 0 ccfl v sw sat voltage (v) 0.6 0.8 1.0 1.2 lt1186f ?g22 0.4 0.2 0.5 0.7 0.9 0.3 0.1 0 0.3 0.6 0.9 1.5 t = 5 c t = 125 c t = 25 c forced beta vs i sw on v sw ccfl i sw (a) 0 forced beta 60 80 110 100 1.6 lt1186f ?g24 40 20 50 70 90 30 10 0 0.4 0.8 1.2 0.2 1.8 0.6 1.0 1.4 2.0 bulb protect servo voltage vs temperature temperature ( c) ?5 bulb protect servo voltage (v) 7.1 7.3 7.5 7.4 7.2 7.0 6.8 6.6 125 150 lt1186f ?g17 6.9 6.7 6.5 ?5 0 ?0 25 50 75 100 175 i ccfl = 10 m a i ccfl = 50 m a i ccfl = 100 m a duty cycle (%) 0 0 ccfl v sw current limit (a) 0.5 1.5 2.0 2.5 20 40 50 90 lt1186f ?g23 1.0 10 30 60 70 80 t = 25 c t = 125 c minimum t = 0 c v sw current limit vs duty cycle v sw sat voltage vs switch current
7 lt1186f typical perfor m a n ce characteristics u w temperature ( c) ?0 output current ( m a) 0 ?5 50 25 75 100 lt1186f ?g25 52 51 50 49 48 v cc = 5v v cc = 3.3v v out = 0v supply voltage (v) 0 output current ( m a) 8 lt1186f ?g26 2 4 6 53 52 51 50 49 48 47 46 45 v out = 0v t j = 25 c output bias voltage (v) ?0 output current ( m a) ?0 ?5 0 ? 5 10 lt1186f ?g27 53 52 51 50 49 48 47 46 45 t j = 25 c v cc = 5v v cc = 3.3v pi n fu n ctio n s uuu ccfl pgnd (pin 1): this pin is the emitter of an internal npn power switch. ccfl switch current flows through this pin and permits internal, switch-current sensing. the regulator provides a separate analog ground and power ground to isolate high current ground paths from low current signal paths. linear technology recommends the use of star-ground layout techniques. i ccfl (pin 2): this pin is the input to the ccfl lamp current programming circuit. this pin internally regulates to 465mv. the pin accepts a dc input current signal of 0 m a to 50 m a full scale from the dac. this input signal is converted to a 0 m a to 250 m a source current at the ccfl v c pin. as input programming current increases, the regu- lated lamp current increases. for a typical 6ma lamp, the range of input programming current is about 0 m a to 50 m a. dio (pin 3): this pin is the common connection between the cathode and anode of two internal diodes. the remain- ing terminals of the two diodes connect to ground. in a grounded-lamp configuration, dio connects to the low voltage side of the lamp. bidirectional lamp current flows in the dio pin and thus the diodes conduct alternately on half cycles. lamp current is controlled by monitoring one- half of the average lamp current. the diode conducting on negative half cycles has one-tenth of its current diverted to the ccfl v c pin. this current nulls against the source current provided by the lamp-current programmer circuit. a single capacitor on the ccfl v c pin provides both stable loop compensation and an averaging function to the half- wave-rectified sinusoidal lamp current. therefore, input programming current relates to one-half of average lamp current. this scheme reduces the number of loop com- pensation components and permits faster loop transient response in comparison to previously published circuits. if a floating lamp configuration is used, ground the dio pin. ccfl v c (pin 4): this pin is the output of the lamp current programmer circuit and the input of the current compara- tor for the ccfl regulator. its uses include frequency compensation, lamp-current averaging for grounded-lamp circuits and current limiting. the voltage on the ccfl v c pin determines the current trip level for switch turn-off. during normal operation this pin sits at a voltage between 0.95v (zero switch current) and 2.0v (maximum switch current) with respect to analog ground (agnd). this pin has a high impedance output and permits external voltage clamping to adjust current limit. a single capacitor to ground provides stable loop compensation. this simpli- fied loop compensation method permits the ccfl regula- tor to exhibit single-pole transient response behavior and virtually eliminates transformer output overshoot. dac i out vs i out bias voltage dac i out vs supply voltage dac i out vs temperature
8 lt1186f pi n fu n ctio n s uuu agnd (pin 5): this is the low current analog ground. it is the negative sense terminal for the internal 1.24v refer- ence and the i ccfl summing voltage in the lt1186f. connect low current signal paths that terminate to ground and frequency compensation components that terminate to ground directly to this pin for best regulation and performance. shdn (pin 6): pulling this pin low causes complete regulator shutdown with quiescent current typically re- duced to 35 m a. if the pin is not used, use a pull-up resistor to force a logic high level (maximum of 6v) or tie directly to v cc . in a shutdown condition, the dac retains its last output current setting and returns to this level when the logic-low signal at the shutdown pin is removed. clk (pin 7): this pin is the shift clock for the dac. this clock synchronizes the serial data and is a schmitt trigger input. in standard spi mode, the clock shifts data into d in and out of d out on the rising and falling edges of the clock respectively. in pulse mode, the rising edge of the clock either increments or decrements the counter. this action depends on the choice of a 1-wire interface (increment only) or a 2-wire interface (increment/decre- ment). cs (pin 8): this pin is the chip select input for the dac. in spi mode, a logic low on the cs pin enables the dac to receive and transfer 8-bit serial data. after the serial input data is shifted in, a rising edge of cs transfers the data into the counter, the dac assumes the new i out value and the d out pin returns to the high impedance state. on power up, a logic high places the dac into pulse mode. pulling cs low after this places the dac into spi mode until v cc resets. d in or up/dn (pin 9): this pin is the digital input for the dac. in spi mode, the 8-bit serial data is shifted into the d in input on each rising edge of the clock signal. in pulse mode, on power up, a logic high at d in transfers the pin function from d in to up/dn, puts the counter into incre- ment-only mode and the pin function shifts to up or down increment control of dac output current. if up/dn re- ceives a logic-low signal, the counter configures to incre- ment/decrement mode until v cc resets. d out (pin 10): this pin is the digital output for the dac. in spi mode, d out is in three-state until cs falls low. the d out pin then serially transfers the previous 8-bit data on every falling edge of the clock. when cs rises high again, d out returns to a three-state condition. in pulse mode, d out is always three-stated. i out (pin 11): this pin is the analog current output for the dac and provides an output current of 50 3 m a over temperature. this pin can be biased from C 20v to 2v for a 3.3v v cc supply voltage or from C 20v to 2.5v for a 5v v cc supply voltage. however, this pin is tied to the i ccfl pin and provides the programming current which sets operat- ing lamp current. the i out pin has very little bias voltage change when it is tied to the i ccfl pin as i ccfl is regulated. the programming current is sourced from the i out pin and sunk by the i ccfl pin. v cc (pin 12): this is the supply pin for the lt1186f. the ic accepts an input voltage range of 3v minimum to 6.5v maximum with little change in quiescent current (zero switch current). an internal, low-dropout regulator pro- vides a 2.4v supply for most of the internal circuitry. supply current increases as switch current increases at a rate approximately 1/50 of switch current. this corre- sponds to a forced beta of 50 for the power switch. the ic incorporates undervoltage lockout by sensing regulator dropout and locking out switching for input voltages below 2.5v. hysteresis is not used to maximize the useful range of input voltage. the typical input voltage is a 3.3v or 5v logic supply. royer (pin 13): this pin connects to the center-tapped primary of the royer converter and is used with the bat pin in a floating-lamp configuration where lamp current is controlled by sensing royer primary-side converter cur- rent. this pin is the inverting terminal of a high-side current sense amplifier. the typical quiescent current is 50 m a into the pin. if the ccfl regulator is not used in a floating-lamp configuration, tie the royer and bat pins together.
9 lt1186f pi n fu n ctio n s uuu bat (pin 14): this pin connects to the battery or ac wall adapter voltage from which the ccfl royer converter operates. this voltage is typically higher than the v cc supply voltage but can equal v cc if v cc is a 5v logic supply. the bat voltage must be at least 2.1v greater than the internal 2.4v regulator or 4.5v. this pin provides biasing for the lamp-current programming block, is used with the royer pin for floating-lamp configurations and connects to one input for the open-lamp protection circuitry. for floating-lamp configurations, this pin is the noninverting terminal of a high-side current sense amplifier. the typical quiescent current is 50 m a into the pin. the bat and royer pins monitor the primary-side royer converter current through an internal 0.1 w topside current sense resistor. a 0a to1a primary-side, center tap converter current is translated to an input signal range of 0mv to 100mv for the current sense amplifier. this input range translates to a 0 m a to 500 m a sink current at the ccfl v c pin that nulls against the source current provided by the programmer circuit. the bat pin also connects to the topside of the internal clamp between the bat and bulb pins that is used for open-lamp protection. bulb (pin 15): this pin connects to the low side of a 7v threshold comparator between the bat and bulb pins. this circuit sets the maximum voltage level across the primary side of the royer converter under all operating conditions and limits the maximum secondary output under start-up conditions or open-lamp conditions. this eases transformer voltage rating requirements. set the voltage limit to ensure lamp start-up with worst-case, lamp start voltages and cold temperature, system operat- ing conditions. the bulb pin connects to the junction of an external divider network. the divider network connects from the center tap of the royer transformer or the actual battery supply voltage to the topside of the current source tail inductor. a capacitor across the top of the divider network filters switching ripple and sets a time constant that determines how quickly the clamp activates. when the comparator activates, sink current is generated to pull the ccfl v c pin down. this action transfers the entire regulator loop from current mode operation into voltage mode operation. ccfl v sw (pin 16): this pin is the collector of the internal npn power switch for the ccfl regulator. the power switch provides a minimum of 1.25a. maximum switch current is a function of duty cycle as internal slope com- pensation ensures stability with duty cycles greater than 50%. using a driver loop to automatically adapt base drive current to the minimum required to keep the switch in a quasi-saturation state yields fast switching times and high efficiency operation. the ratio of switch current to driver current is about 50:1. test circuits 3k 100pf lt1186f ?tc02 5v t dz waveform 2, t dv t dz waveform 1 d out load circuit for t dz , t dv load circuit for t do 3k 100pf lt1186f ?tc01 1.4v d out voltage waveforms for t dz , t dv 0.8v 0.4v 2.4v lt1186f ?tc03 d out clk t do voltage waveforms for t do lt1186f ?tc04 0.8v cs d out waveform 1 (see note 1) d out waveform 2 (see note 2) 2.4v 2.0v 90% 10% 0.4v t dv t dz note 1: waveform 1 is for an output with internal conditions such that the output is high unless disabled by cs note 2: waveform 2 is for an output with internal conditions such that the output is low unless disabled by cs
10 lt1186f block diagra m w lt1186f dac programmable ccfl switching regulator comp under- voltage lockout thermal shutdown 2.4v regulator shutdown 200khz osc 6 i ccfl agnd dio bulb ccfl v c ccfl pgnd 50 m a full scale ccfl v sw royer bat v cc logic drive gain = 4.4 q3 2 q5 1 q4 5 q8 1 q10 2 r1 0.125 w r4 0.1 w q6 2 r3 1k d2 6v d1 q11 q1 13 14 12 q7 9 q9 3 25 3 15 4 16 1 v1 0.465v + ccfl 0 m a to 50 m a from i out + g m + current amp anti- sat lt1186f ?bd shutdown latch and logic latch and logic 8-bit current dac clk shdn clk q9 do(lsb) up/dn 8-bit counter/register i out d out 8 8 8 9-bit shift register voltage reference shdn mode select 0 = pulse 1 = spi power-on reset control logic clk d in cs up only/ up/dn 7 9 8 11 10
11 lt1186f applicatio n s i n for m atio n wu u u introduction current generation portable computers and instruments use backlit liquid crystal displays (lcds). cold cathode fluorescent lamps (ccfls) provide the highest available efficiency in back lighting the display. providing the most light out for the least amount of input power is the most important goal. these lamps require high voltage ac to operate, mandating an efficient high voltage dc/ac con- verter. the lamps operate from dc, but migration effects damage the lamp and shorten its lifetime. lamp drive should contain zero dc component. in addition to good efficiency, the converter should deliver the lamp drive in the form of a sine wave. this minimizes emi and rf emissions. such emissions can interfere with other de- vices and can also degrade overall operating efficiency. sinusoidal ccfl drive maximizes current-to-light conver- sion in the lamp. the circuit should also permit lamp intensity control from zero to full brightness with no hysteresis or pop-on. the small size and battery-powered operation associated with lcd equipped apparatus dictate low component count and high efficiency for these circuits. size con- straints place severe limitations on circuit architecture and long battery life is a priority. laptop and handheld portable computers offer an excellent example. the ccfl and its power supply are responsible for almost 50% of the battery drain. additionally, all components, including pc board and hardware, usually must fit within the lcd enclosure with a height restriction of 5mm to 10mm. the ccfl regulator drives an inductor that acts as a switched-mode current source for a current-driven royer- class converter with efficiencies as high as 90%. the control loop forces the ccfl pwm to modulate the aver- age inductor current to maintain constant current in the lamp. the constant current value, and thus lamp intensity, is programmable. this drive technique provides a wide range of intensity control. a unique lamp-current pro- gramming block permits either grounded lamp or floating lamp configurations. grounded lamp circuits directly sense one-half of average lamp current. floating lamp circuits directly sense the royers primary-side converter current. floating-lamp circuits provide symmetric differential drive to the lamp and reduce the parasitic loss from stray lamp- to-frame capacitance, extending illumination range. block diagram operation the lt1186f is a fixed frequency, current mode switching regulator. a fixed frequency, current mode switcher con- trols switch duty cycle directly by switch current rather than by output voltage. referring to the block diagram for the lt1186f, the switch turns on at the start of each oscillator cycle. the switch turns off when switch current reaches a predetermined level. the control of output lamp current is obtained by using the output of a unique programming block to set current trip level. the current mode switching technique has several advantages. first, it provides excellent rejection of input voltage variations. second, it reduces the 90 phase shift at mid-frequencies in the energy storage inductor. this simplifies closed-loop frequency compensation under widely varying input volt- age or output load conditions. finally, it allows simple pulse-by-pulse current limiting to provide maximum switch protection under output overload or short-circuit condi- tions. the lt1186f incorporates a low dropout internal regula- tor that provides a 2.4v supply for most of the internal circuitry. this low dropout design allows input voltage to vary from 3v to 6.5v with little change in quiescent current. an active low shutdown pin typically reduces total supply current to 35 m a by shutting off the 2.4v regulator and locks out switching action for standby operation. the ic incorporates undervoltage lockout by sensing regulator dropout and locking out switching below about 2.5v. the regulator also provides thermal shutdown protection that locks out switching in the presence of excessive junction temperatures. a 200khz oscillator is the basic clock for all internal timing. the oscillator turns on the output switch via its own logic and driver circuitry. adaptive anti-sat circuitry detects the onset of saturation in the power switch and adjusts base drive current instantaneously to limit switch saturation. this minimizes driver dissipation and provides rapid turn- off of the switch. the ccfl power switch is guaranteed to provide a minimum of 1.25a in the lt1186f. the anti-sat
12 lt1186f applicatio n s i n for m atio n wu u u circuitry provides a ratio of switch current to driver current of about 50:1. 8-bit current output dac the 8-bit current output dac is guaranteed monotonic and is digitally adjustable by the 8-bit counter in 256 equal steps. on power up, the counter resets to 80h and the dac assumes its mid-range value. the current output i out drives the i ccfl pin and sets control current for the lamp current programming block. the dac has its own 1.24v bandgap reference and a voltage to current converter that is trimmed at wafer sort to provide the precision full-scale current reference. over temperature, the current output of the dac is 50 m a 6%. digital interface on power-up, a logic high at cs configures the dac into pulse mode. if cs is ever pulled low, the chip configures into spi mode until v cc resets. on power-up in pulse mode, a logic high at d in puts the counter into increment- only mode. if up/dn (d in ) is ever pulled low, the counter configures into increment/decrement mode until v cc re- sets. these modes are illustrated in figure 1. single dac spi mode pulse mode lt1186f ?f01a increment/ decrement increment- only cs stays high cs ever goes low d in (up/dn) ever goes low d in stays high figure 1a. tree diagram (lt1186f dac operating modes) figure 1b. spi mode setup power on v cc lt1186f ?f01b cs cs ever goes low power on v cc lt1186f ?f01c cs always high d in always high figure 1c. pulse mode setup (increment only) power on v cc cs always high lt1186f ?f01d up/dn up/dn ever goes low figure 1d. pulse mode setup (increment/decrement) standard spi mode refer to the serial interface operating sequence in figure 2. a falling edge at cs initiates the data transfer. after the falling cs is recognized, d out comes out of three-state. the clock (clk) synchronizes the data transfer. each input bit shifts into d in beginning with the msb on the rising clk edge and each previous data bit shifts out of d out begin- ning with the msb on the falling clk edge. after the 8-bit serial input data is shifted in, a rising edge at cs transfers the data into the counter, the dac assumes the new value i out = (8-bit serial input data)(50 m a)/255 and the d out pin returns to a high impedance state. 1-wire interface (pulse mode) in increment-only pulse mode, each rising edge of clk increments the upper six bits of the counter by one count. when incremented beyond 11111100b, the counter rolls over and sets the dac to the minimum value 00000000b. therefore, a single pulse applied to clk increases the upper 6-bit counter by one-step, and 63 pulse applied to clk decreases the counter by one-step. the last two lsbs are always zero in this mode. i out = (b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ) (50 m a)/255. the upper 6-bit counter = b 7 b 6 b 5 b 4 b 3 b 2 and b 1 = b 0 = 0. to configure the lt1186f into increment-only mode, tie cs and d in to v cc .
13 lt1186f applicatio n s i n for m atio n wu u u figure 2. spi interface timing specification d in clk cs d7 d6 d5 d4 d3 d2 d1 d0 hi-z d7 d6 d5 d4 d3 d2 d1 d0 d7 t dz hi-z lt1186f ?f02 d out t do t ckhi t dh t ds t css t cks t cslo t dv t cklo t csh t cshi t ckh 2-wire interface (pulse mode) in increment/decrement pulse mode, a logic high at up/ dn programs the counter into increment mode and each rising edge of clk increments the upper six bits of the counter by one. the counter stops incrementing at 11111100b. a logic low at up/dn programs the counter into decrement mode and each rising edge of clk decre- ments the upper six bits of the counter by one. the counter stops decrementing at 00000000b. the last two lsbs are always zero in this mode. i out = (b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 ) (50 m a)/255. the upper 6-bit counter = b 7 b 6 b 5 b 4 b 3 b 2 and b 1 = b 0 = 0. to configure the lt1186f into increment/ decrement mode, tie cs to v cc and pulse the up/dn pin once on power-up. simplified lamp current programming a programming block in the lt1186f controls lamp current, permitting either grounded lamp or floating lamp configurations. grounded configurations control lamp current by directly controlling one-half of actual lamp current and converting it to a feedback signal to close a control loop. floating configurations control lamp current by directly controlling the royers primary-side converter current and generating a feedback signal to close a control loop. previous backlighting solutions have used a traditional error amplifier in the control loop to regulate lamp current. this approach converted an rms current into a dc voltage for the input of the error amplifier. this approach used several time constants in order to provide stable loop frequency compensation. this compensation scheme meant that the loop had to be fairly slow and that output overshoot with start-up or overload conditions had to be carefully evaluated in terms of transformer stress and breakdown voltage requirements. the lt1186f eliminates the error amplifier concept en- tirely and replaces it with a lamp current programming block. this block provides an easy-to-use interface to program lamp current. the programmer circuit also re- duces the number of time constants in the control loop by combining the error signal conversion scheme and fre- quency compensation into a single capacitor. the control loop thus exhibits the response of a single pole system, allows for faster loop transient response and virtually eliminates overshoot under start-up or overload condi- tions. lamp current is programmed at the input of the program- mer block, the i ccfl pin. this pin is the input of a shunt regulator and accepts a dc input current signal of 0 m a to 50 m a from the dac. this input signal is converted to a 0 m a to 250 m a source current at the ccfl v c pin. the program- mer circuit is simply a current-to-current converter with a gain of five. the typical input current programming range for 0ma to 6ma lamp current is 0 m a to 50 m a. the i ccfl pin is sensitive to capacitive loading and will oscillate with capacitance greater than 10pf. for example, loading the i ccfl pin with a 1 or 10 scope probe causes oscillation and erratic ccfl regulator operation because of the probes respective input capacitance. a current meter in series with the i ccfl pin will also produce oscil-
14 lt1186f applicatio n s i n for m atio n wu u u lation due to its shunt capacitance. use a decoupling resistor of several kilohms between the i ccfl pin and the i out pin if excessive trace stray capacitance exists. nor- mally, this resistor is not required. in some applications, the maximum programming current required at the i ccfl pin for a maximum lamp current will be less than the full-scale output current of the dac, which is 50 m a. the system designer can either limit the maximum programming current through software built into the system, or use a current splitter which shunts a percentage of the full- scale current from the i ccfl pin. a splitter circuit is illustrated in figure 3. a divider string is used from a reference voltage to set up a voltage level equal to the i ccfl summing voltage, or 465mv. the main current flowing in the divider string should be chosen to swamp out the effects of the shunted current into the divider string. the transfer function between lamp current and input programming current must be empirically determined and is dependent on the particular lamp/display housing com- bination used. the lamp and display housing are a distrib- uted loss structure due to parasitic lamp-to-frame capaci- tance. this means that the current flowing at the high- voltage side of the lamp is higher than what is flowing at the dio pin side of the lamp. the input programming current is set to control lamp current at the high-voltage side of the lamp, even though the feedback signal is the lamp current at the bottom of the lamp. this ensures that the lamp is not overdriven which can degrade the lamps operating lifetime. therefore, the full scale current of the dac does not necessarily correspond to the current re- quired to set maximum lamp current. floating lamp configuration in a floating lamp configuration, the lamp is fully floating with no galvanic connection to ground. this allows the transformer to provide symmetric differential drive to the lamp. balanced drive eliminates the field imbalance asso- ciated with parasitic lamp-to-frame capacitance and re- duces thermometering (uneven lamp intensity along the lamp length) at low lamp currents. carefully evaluate display designs in relation to the physi- cal layout of the lamp, its leads and the construction of the display housing. parasitic capacitance from any high voltage point to dc or ac ground creates paths for unwanted current flow. this parasitic current flow de- grades electrical efficiency and losses up to 25% have been observed in practice. as an example, at a royer operating frequency of 60khz, 1pf of stray capacitance represents an impedance of 2.65m w . with an operating lamp voltage of 400v and an operating lamp current of 6ma, the parasitic current is 150 m a. this additional cur- rent must be supplied by the transformer secondary. layout techniques that increase parasitic capacitance include long high voltage lamp leads, reflective metal foil around the lamp and displays supplied in metal enclo- sures. losses for a good display are under 5%, whereas, losses for a bad display range from 5% to 25%. lossy displays are the primary reason to use a floating lamp configuration. providing symmetric, differential drive to the lamp reduces the total parasitic loss by one-half. i out full-scale 50 m a v(i ccfl ) 465mv i xi v1 r1 v ref r3 i = 50 m a 0 < x < 1 select v1 within the dac i out compliance range (ex. v1 = 2v for v cc = 3.3v or 5v) choose i1 >> (1 ?x)i r1 = (v1 ?0.465)/(x)(50 m a) r2 = (v1 ?0.465)/(1 ?x)(50 m a) r3 = (v ref ?0.465)/i1 r4 = 0.465r3/[(1 ?x) 50 m ar3 + (v ref ?0.465)] i1 lt1186f ?f03 r4 v(i ccfl ) (1 ?x)i r2 figure 3 grounded lamp configuration in a grounded lamp configuration, the low voltage side of the lamp connects directly to the lt1186f dio pin. this pin is the common connection between the cathode and anode of two internal diodes. in previous grounded lamp solutions, these diodes were discrete units and are now integrated onto the ic, saving cost and board space. bidirectional lamp current flows in the dio pin and thus, the diodes conduct alternately on half cycles. lamp cur- rent is controlled by monitoring one-half of the average lamp current. the diode conducting on negative half cycles has one-tenth of its current diverted to the ccfl pin and nulls against the source current provided by the lamp current programmer circuit. the compensation capacitor on the ccfl v c pin provides stable loop compensation and an averaging function to the rectified sinusoidal lamp current. therefore, input programming current relates to one-half of average lamp current.
15 lt1186f applicatio n s i n for m atio n wu u u maintaining closed-loop control of lamp current in a floating lamp configuration necessitates deriving a feed- back signal from the primary side of the royer trans- former. previous solutions have used an external preci- sion shunt and high-side sense amplifier configuration. this approach has been integrated onto the lt1186f for simplicity of design and ease of use. an internal 0.1 w resistor monitors the royer converter current and con- nects between the input terminals of a high-side sense amplifier. a 0 C 1 amp royer primary-side, center-tap current is translated to a 0 m a to 500 m a sink current at the ccfl v c pin to null against the source current provided by the lamp current programmer circuit. the compensation capacitor on the ccfl v c pin provides stable loop com- pensation and an averaging function to the error sink current. therefore, input programming current is related to average royer converter current. floating lamp circuits operate similarly to grounded lamp circuits except for the derivation of the feedback signal. the transfer function between lamp current and input programming current must be empirically determined and is dependent upon a myriad of factors including lamp characteristics, display construction, transformer turns ratio and the tuning of the royer oscillator. once again, lamp current will be slightly higher at one end of the lamp and input programming current should be set for this higher level to ensure that the lamp is not overdriven. the internal 0.1 w high-side sense resistor on the lt1186f is rated for a maximum dc current of 1a. this resistor can be damaged by extremely high surge currents at start-up. the royer converter typically uses a few microfarads of bypass capacitance at the center tap of the transformer. this capacitor charges up when the system is first pow- ered by the battery pack or an ac wall adapter. the amount of current delivered at start-up can be very large if the total impedance in this path is small and the voltage source has high current capability. linear technology recommends the use of an aluminum electrolytic for the transformer center-tap bypass capacitor with an esr greater than or equal to 0.5 w . this lowers the peak surge currents to an acceptable level. in general, the wire and trace inductance in this path also help reduce the di/dt of the surge current. this issue only exists with floating lamp circuits as grounded lamp circuits do not make use of the high-side sense resistor. input capacitor type caution must be used in selecting the input capacitor type for switching regulators. aluminum electrolytics are elec- trically rugged and the lowest cost, but are physically large to meet required ripple current ratings, and size con- straints (especially height) may preclude their use. ce- ramic capacitors are now available in larger values and their high ripple current and voltage rating make them ideal for input bypassing. cost is fairly high and footprint can be large. solid tantalum capacitors would be a good choice except for a history of occasional failure when subjected to large current surges during start-up. the input bypass capaci- tor of regulators can see these high surges when a battery or high capacitance source is connected. some manufac- turers have developed tantalum capacitor lines specially tested for surge capability (avx tps series for instance), but even these units may fail if the input voltage surge approaches the capacitors maximum voltage rating. avx recommends derating the capacitor voltage by 2:1 for high surge applications. applications support linear technology invests an enormous amount of time, resources and technical expertise in understanding, de- signing and evaluating backlight/lcd contrast solutions for system designers. the design of an efficient and compact lcd backlight system is a study of compromise in a transduced electronic system. every aspect of the design is interrelated and any design change requires complete re-evaluation for all other critical design param- eters. linear technology has engineered one of the most complete test and evaluation setups for backlight designs and understands the issues and tradeoffs in achieving a compact, efficient and economical customer solution. linear technology welcomes the opportunity to discuss, design, evaluate and optimize any backlight/lcd contrast system with a customer. for further information on back- light/lcd contrast designs, consult the references. information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
16 lt1186f applicatio n s i n for m atio n wu u u linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax : (408) 434-0507 l telex : 499-3977 ? linear technology corporation 1995 references 1. williams, jim. august 1992. illumination circuitry for liquid crystal displays . linear technology corporation, application note 49. 2. williams, jim. august 1993. techniques for 92% effi- cient lcd illumination . linear technology corporation, application note 55. 3. bonte, anthony. march 1995. lt1182 floating ccfl with dual polarity contrast . linear technology corpora- tion, design note 99. 4. williams, jim. april 1995. a precision wideband cur- rent probe for lcd backlight measurement . linear tech- nology corporation, design note 101. 5. lt1182/lt1183/lt1184/lt1184f data sheet. ccfl/ lcd contrast switching regulators . april 1995. linear technology corporation. dimensions in inches (millimeters) unless otherwise noted. package descriptio n u lt/gp 1096 7k rev a ? printed in usa part number description comments lt1107 micropower dc/dc converter for lcd contrast control 1a, 63khz, hysteretic lt1172 current mode switching regulator for ccfl or lcd contrast control 1.25a, 100khz lt1173 micropower dc/dc converter for lcd contrast control 1a, 24khz, hysteretic lt1182 dual current mode switching regulator for ccfl and lcd contrast control 1.25a, 0.625a, 200khz lt1183 dual current mode switching regulator for ccfl and lcd contrast control 1.25a, 0.625a, 200khz lt1184 current mode switching regulator for ccfl control 1.25a, 200khz lt1184f current mode switching regulator for ccfl control 1.25a, 200khz lt1372 current mode switching regulator for ccfl or lcd contrast contol 1.5a, 500khz related parts s package 16-lead plastic small outline (narrow 0.150) (ltc dwg # 05-08-1610) 0.016 ?0.050 0.406 ?1.270 0.010 ?0.020 (0.254 ?0.508) 45 0 ?8 typ 0.008 ?0.010 (0.203 ?0.254) 1 2 3 4 5 6 7 8 s16 0695 0.150 ?0.157** (3.810 ?3.988) 16 15 14 13 0.386 ?0.394* (9.804 ?10.008) 0.228 ?0.244 (5.791 ?6.197) 12 11 10 9 0.053 ?0.069 (1.346 ?1.752) 0.014 ?0.019 (0.355 ?0.483) 0.004 ?0.010 (0.101 ?0.254) 0.050 (1.270) typ dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * **

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